Global Instruction Selection

This document is a work in progress. It reflects the current state of theimplementation, as well as open design and implementation issues.

GlobalISel is a framework that provides a set of reusable passes and utilitiesfor instruction selection — translation from LLVM IR to target-specificMachine IR (MIR).

GlobalISel is intended to be a replacement for SelectionDAG and FastISel, tosolve three major problems:

• Performance — SelectionDAG introduces a dedicated intermediaterepresentation, which has a compile-time cost.

GlobalISel operates on the whole function.

• Modularity — SelectionDAG and FastISel are radically different and sharevery little code.

GlobalISel is built in a way that enables code reuse. For instance, both theoptimized and fast selectors share the Core Pipeline, and targets canconfigure that pipeline to better suit their needs.

More information on the design and implementation of GlobalISel can be found inthe following sections.

• Generic Opcodes
• Porting GlobalISel to A New Target

• IRTranslator
• RegBankSelect

The initial goal is to replace FastISel on AArch64. The next step will be toreplace SelectionDAG as the optimized ISel.

:While we iterate on GlobalISel, we strive to avoid affecting the performance ofSelectionDAG, FastISel, or the other MIR passes. For instance, the types ofGeneric Virtual Registers are stored in a separate table in ,that is destroyed after .

For the initial FastISel replacement, we intend to fallback to SelectionDAG onselection failures.

:We considered never having a fallback to SelectionDAG, instead deciding earlywhether a given function is supported by GlobalISel or not. The decision wouldbe based on Legalizer queries.We abandoned that for two reasons:a) on IR inputs, we’d need to basically simulate the ;b) to be robust against unforeseen failures and to enable iterativeimprovements.